M.Tech (VLSI & Embedded Systems)

PAL_3296 PAL_3296

M.Tech VLSI Lab is equipped with industry standard EDA tool from Cadence Design System. Students will explore the CAD tool and understand the flow of Full Custom IC design cycle. Both analog and digital designs are implemented in this Lab. Digital circuits such as inverter, buffer, transmission gate, flip flop, counters are simulated and verification using CADENCE NC Sim tool. Students develop Verilog Code for the front end design of digital circuits like different types of adders, multipliers, comparator, LFSR, parity generator, universal shift registers and state machine design. Digital circuits are implemented using Xilinx FPGA devices. Analog designs such as inverter, CS, differential Amp, Op-Amp, integrator and R-2R DAC are developed and checked for DRC, LVS and Parasitic Extraction are carried out using cadence tools. The Pre layout and Post layout simulation are performed under virtuoso environment; tool Assura supports the design rule check, layout versus schematic check and extraction of parasitic which are required for Post layout simulation. The Mixed signal simulations are performed using AMS Designer.  Students develop assembly language and embedded C coding to explore ARM- Cortex M3 with support of Keil uVision for different applications such as buzzer, temperature sensor, LCD display, stepper motor and  to display message