This post was last updated on July 9th, 2021
Dr. Veena S Chakravarthi
Designation :Head -Research and Adjunct Professor
Area of specialization :VLSI
Date of Joining BNMIT :2/19/2010
Nature of Association (Regular/Contractual/Adjunct) :Adjunct
E-mail Id : veenasc@bnmit.in
No. of years of Experience :30
Qualification
| Degree | Institution | Month & Year of Passing |
| PhD in Electronics |
Experience
- 25 years of Industry and 10 years of academics and research
| SI. No. | Designation | Institution | Duration |
- Inventor of Conceptual health watch Patent granted by USPTO
- Inventor of Design patent registered on SenseH device
- Awards and Achievements
- Co guided a candidate for PhD
- Guiding 4 research scholars for their PhD degree
- Initiated Project Bhageerathi, Chip development project in BNMIT
Expertise/Subjects handled
- VLSI and system on chip architect.
Subjects taught:
- VLSI design
- Verilog HDL
- Advances in VLSI design
- Low power VLSI design
- SOC Design
- VLSI Design verification
- Research Methodology and IPR
- Analog and Mixed mode VLSI design
- IOT and WSN
Research Interest
- Low power system on chip design architectures
- Open source RISC V architectures
- Funding received: VTU-VGST grant of Rs.17 Lakhs for load aware low power multi drive standard cell library design
- Enrolled BNMIT under HEP program of Mentor Graphics, a Siemens business through which has access to EDA tool set.
- Patents filed and their status:
| Sl. No | Title | Status | Country | Inventors | Owner | Application /Grant number |
| 1 | Smart Wearable device health for Watch | Granted | US | Veena, Praveen, Vishy | Sensesemi Technologies Pvt. Ltd. | 10194862 |
| 2 | Smart wearable device for health watch | Filed | India | Veena, Vishy, Praveen D | Sensesemi Technologies Pvt.Ltd | 201644033347 |
| 3 | Multipurpose portable healthcare device | Registered | India | Veena, Vijay, Vishy | Sensesemi Technologies Pvt.Ltd | 320547-001 |
| 4 | Smart handheld health monitoring device | Filed | India | Veena, Vijay, Vishy, Nidhin | Sensesemi Technologies Pvt. Ltd | 201941037998 |
| 5 | Method for clinical grade ECG monitoring | Filed | India | Veena, Vijay, Vishy, Suhasini S | Sensesemi Technologies Pvt.Ltd | |
| 6 | Method for clinical grade ECG monitoring | Filed | US | Veena, Vijay, Vishy, Suhasini S | Sensesemi Technologies Pvt. Ltd | |
| 7 | Method, System and Apparatus for Asynchronous SOC Testing and Validation” | Filed | India | Veena, YashaJyothi M Shirur, M. S Suresh | BNMIT | 201641022110 |
Books and Book Chapters
- Authored a book on “A Practical Approach to VLSI System on Chip (SoC) Design”published by Springer Nature 2019
- Book chapter on “ Digital-Controlled Dual-Mode Switching Mode Power Supply for Low-Power Applications” in Advances in Bioinformatics, Multimedia, and Electronics Circuits and Signals”
- Book chapters: “Design of Error Correction Engine Based on Flexible Unequal Error Control Code (FUEC) for Flash Memory Faults in Space Applications” in book Advances in Communication, Signal Processing, VLSI, and Embedded Systems, Springer DOI 978-981-15-0626-0_33, © 2020
- Edited “Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking (VCASAN-2013)” published by Springer
Technical Paper publications
| Chakravarthi, Veena S; | SOC Design Verification |
| Bee, Hajeera; Chakravarthi, Veena S; | Design and Verification of Scalable, Re-usable 16-Point IFFT Core for DSP Engine |
| Shirur, Yasha Jyothi M; Lakshmi, HR; Chakravarthi, Veena S; | Implementation of Area Efficient Hybrid MBIST for Memory Clusters in Asynchronous SoC |
| Chakravarthi, Veena S; | SOC Physical Design |
| Rao, Shubha; Prabhu, Abhinav; Chakravarthi, Veena S; | Design of FPGA-based sliding mode controller for low-voltage high-frequency buck converter |
| Chakravarthi, Veena S; Burli, Satish; | Architecting 802.11 ad WLAN SoC for best performance |
| Rajapurohit, Vaibhav; Chakravarthi, Veena S; | Designing low power high throughput MAC for 802.11 AD WLAN SoC |
| Rao, K Shubha; Chakravarthi, Veena S; | FPGA implementation of voltage regulator module for system on chip |
| Mamatha, S; Rao, K Shubha; Chakravarthi, Veena S; | FPGA Based Digital Controller for DC-DC Buck Converter |
| Chakravarthi, Veena S; | Platform SOC for SMART Home |
| Chakravarthi, Veena S; | SOC Physical Design Verification |
| Shirur, YJM; Chakravarthi, VS; | Design and Implementation of Power Efficient Micro Pipelined GALS Based 2-D FFT Processor Core |
| Chakravarthi, Veena S; Shirur, Yasha Jyothi M; Rekha, P; | Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking (VCASAN-2013) |
| Chakravarthi, Veena S; | SOC Packaging |
| Chakravarthi, Veena S; Dodagoudar, Praveen; Mundkur, Vishweshwara; | Smart wearable device for health watch |
| Deepthi, P; Chakravarthi, Veena S; | Design of novel Vedic asynchronous digital signal processor core |
| Chakravarthi, Veena S; | System on Chip (SOC) Design |
| Chakravarthi, Veena S; | Static Timing Analysis (STA) |
| Chakravarthi, Veena S; | A Practical Approach to VLSI System on Chip (SoC) Design |
| Shirur, Yasha Jyothi M; Bhimashankar, Bilure Chetana; Chakravarthi, Veena S; | Performance analysis of low power microcode based asynchronous P-MBIST |
| Chakravarthi, Veena S; | SOC Constituents |
| Kumar, DN Krishna; Rajan, Ramya S; Chakravarthi, Veena S; | Determining Standard Cell Drive Strength Based on On-Chip Load Assessment |
| Shirur, Yasha Jyothi M; Chakravarthi, Veena S; Varchaswini, R; | Adder-Based Address Generation for Embedded MBIST |
| Rao, K Shubha; Chakravarthi, Veena S; | Digital-Controlled Dual-Mode Switching Mode Power Supply for Low-Power Applications |
| Chakravarthi, Veena S; Shilpa, M; | Ingress flow based triple token bucket traffic control system for distributed networks |
| Rao, Shubha; Chakravarthi, Veena S; | Design and Performance Analysis of Digital Control Laws for Low Power High Frequency Switching Power Supply |
| Chakravarthi, Veena S; Bhaskar, Rashmi S; Kusanur, Vrunda; | Conceptual frame work of smart WSN for Bangalore urban environment monitoring |
| Parveez Ahamed, RJ; Chakravarthi, Veena S; Srinivasan, N; | System Verilog Based Verification Methodology for SoC at IP Level |
| Chakravarthi, Veena S; | SOC Synthesis |
| Ajay, G; Rajan, Ramya; Chakravarthi, Veena S; | Accurate power measurement methodology for VLSI circuits using CAD tools |
| Chakravarthi, Veena S; Ghosh, Swaroop; | Circuit Design Methodologies for Test Power Reduction in Nano-Scaled Technologies |
| Shree, G Amrutha; Chakravarthi, Veena S; | Design of Error Correction Engine Based on Flexible Unequal Error Control Code (FUEC) for Flash Memory Faults in Space Applications |
Hobbies
Sports
Music
Any other things
- Voracious reader, Technology tracker and blogger
- Co-founder and CTO of Sensesemi Technologies Pvt. Ltd., Bangalore
- Vice Chair, IEEE nanotech council, Bangalore Section
- Consultant Prodigy technovations Bangalore Jan 2019-June 2019
- Was part of panel discussion on“demystifying Covid-19 and ways to deal with it’, organised by IIHMR and BNMIT
- Delivered keynote address on “Role of Industry in enhancing the quality of academic delivery” during IEEE Industry Academia Conclave-IAC 2020, a flagship event of IEEE PES, Bangalore Section
- Created virtual stall for Sensesemi Technologies sponsored by startup Karnataka in Vision summit 2020 organised by IESA Bangalore.
