This post was last updated on       March 4th, 2021

Dr. Yasha Jyothi M Shirur


Designation : Professor

Area of specialization :VLSI Design, Design for Testability

Date of Joining BNMIT : 8/11/2003

Nature of Association (Regular/Contractual/Adjunct) :Regular

E-mail Id :yashajyothimshirur@bnmit.in 

No. of years of Experience :20

Qualification: PhD

DegreeInstitutionMonth & Year of Passing
PhDECE Research Centre, BNMIT /VTUJuly, 2017
M. TechBMSCE, Bengaluru/VTUJune 2004
B. EB.I.ET, Davangere/ Kuvempu UniversityJune 1997

 

Experience: 20

  • Teaching – 20
  • Industry – Nil

 

Sl  No.DesignationInstitutionDuration
1.ProfessorBNMIT, Bengaluru3 years 10 months (Till Date
2.Associate ProfessorBNMIT, Bengaluru5 Years
3.Assistant ProfessorBNMIT, Bengaluru4Year 2 Months
4.Lecturer/Sr. LecturerBNMIT, Bengaluru4Year 2 Months
5.Teaching Asst.DSCE, Bengaluru1 Year 4 Months
6.FacultyCMS Computer Institute, Davangere1 Year 1.5 Months

Awards and Achievements

  1. Best Paper Award for the paper“Performance evaluation of Distributed Arithmetic based MAC Structures for DSP Applications” in 7th International Virtual Conference on Smart Structures and Systems (ICSSS 2020) organized by Saveetha Engineering College, Chennai. Tamil Nadu, India on 23rd and 24th of July 2020.
  2. Best Paper-Fourth Prize for the paper “Low Power High Speed Vedic Techniques in Recent VLSI Design – A Survey” in 1stAll India Paper writing competition on Emerging Research (PACER) 2020, organized by WorldServe Online held in July 2020.
  3. Merit Awardreceived while pursuing M. Tech in 2003 at BMSCE, Bangalore.
  4. Best Oral Presenter Awardfor Best Presentation in International Conference of Communication and Signal Processing (ICCSP-2014), Bangkok, Thailand

Internship/SDP Conducted

  1. Under Skillbot company conducted 6 weeks internship on Project based Digital design Modelling using Verilog for PG students from 17-8-2020 to 26-9-2020.
  2. Conducted 50 hours (10 days – 5 hours per day) Skill development program on “Digital Design Modelling Using Verilog HDL” from 27-7-2020 to 8-8-2020.

Invited Talks

  1. Book Review on: “A Practical Approach to VLSI System on Chip (SoC) Design” under Webinar Series on Nanotechnolgy organised by IEEE-BNMIT in association with Nanotechnology Council on 19-11-2020.
  2. “Research and Professional Development” organized on Faculty Induction Program from 22nd & 23rd September 2020.
  3. “Online Education- Pros and Cons” Organized by IEEE BNMIT Student Branch in association With IEEE Nanotechnology Council, Bengaluru on 1-6-2020.

Editorial/Technical/Reviewer

  1. International Journal of Engineering Research & Technology (IJERT)
  2. Technical Committee: International Conference on Computer and Communications ICCC-IEEE on December 06-09, 2019 in Chengdu, China.

Session Chair/ Judge

  1. Judge for Mock Paper Presentation organized by IEEE-BNMIT Student Branch in association with IEEE Nanotech Council on 17th October 2020.

Expertise/Subjects handled

UG

  • Basic Electronics
  • Analog electronics
  • Digital Electronics
  • Network Analysis
  • Linear Integrated circuits and applications
  • Digital design using Verilog Transmission lines and Wave Guides
  • Information Theory and Coding
  • VLSI Design
  • Principles of Communication Systems Digital Communication
  • Programming with C++
  • Cryptography and Network Security

PG

  • Digital VLSI Design
  • Analog Mixed mode VLSI Design
  • High Speed VLSI Design
  • VLSI Testing and Testability
  • VLSI Technology
  • Advanced VLSI design
  • Low Power VLSI design
  • Testing of VLSI circuits
  • SoC Design
  • ASIC Design
  • VLSI System Design

Research Interest:

  • VLSI Design
  • Design for Testability
  • Low Power VLSI Design
  • Embedded Systems

Patent Filed:

  • Patent Published with patent no: 201641022110.
  • Title: “Method, System and Apparatus for Asynchronous SoC Testing and Validation”
  • Inventors: Yasha Jyothi M Shirur, Dr. M. S. Suresh, Dr. Veena S Chakravarthi.

Funding received

Nil

Publications: 45

International Journals: 22

  • July 2020 – June 2021:
  • Muskan Tated, Sri Haripriya Rai N, Bindu S, Yasha Jyoti M Shirur “Nano Electronics and it’s Wide Applications” got published in GIS Science Journal with ISSN No: 1869-9391; VOLUME 7, ISSUE 12, Dec 2020, PP 436-445, Impact factor: 6.1 (Scopus Indexed Journal).
  • Sahil, Soumita Paul, Yasha Jyothi M Shirur “Power Optimization Techniques adopted at various abstraction levels in system on Chip Design- A Survey” got published in International Journal for Research in Applied Science & Engineering Technology (IJRASET) ISSN:2321-9653; IC value:45.98, SJ Impact factor:7.429 (Volume 8 Issue X) Oct 2020.
  • Deepa S. Yasha Jyothi M Shirur “Design of flexible FFT core for fast computing of digital signals in real time applications”got published in International Journal of Advance Research, Ideas and Innovations in Technology (IJARIIT) ISSN: 2454-132X Impact factor: 6.078 (Volume 6, Issue 4) pp 127-131 July 2020.
  • Swathi Dayananda, Varshitha K. R, Rohini T, Yasha Jyothi M Shirur, Jyothi Munavalli, “Low Power High Speed Vedic Techniques in Recent VLSI Design – A Survey” got published inPerspectives in Communication, Embedded-Systems and Signal-Processing (PiCES) – An International Journal with ISSN: 2566-932X. PP 34-43. July 2020.
  • July 2019-June 2020:
  • L. Lahari, M. Bharathi, Yasha Jyothi M ShirurA Review on Distributed Arithmetic and Offset Binary Coding” got published in i-manager’s Journal on Digital Signal Processing, Vol. 7 No. 3lJuly – September 2019 PP 27-34.
  • Anshu Kumar, Nisarga U, Yasha Jyothi M Shirur “Design and Development of Beach Sand Cleansing Equipment Based on Electro-Hydraulic Mechanism”got published in International Journal of Advanced Science and Technology (IJAST), ISSN No. 2005-4238 Volume 29 No. 12 PP 163-170 (Scopus Indexed).
  •  July 2018 – June 2019:
  • Yasha Jyothi M Shirur “Efficient Method to Measure Dynamic Temperature Variations in a Non-Uniform Heat Dissipated Integrated Chip”got published in International Journal of Computer Sciences and Engineering. (IJCSE) Vol.-7, Issue-6, June 2019 (UGC Approved).
  • Yasha Jyothi M Shirur, Harshitha A “An Efficient Radix-3 Multiplier less 2D Convolution Filter for Visual Search Applications”got published in International Journal of Scientific Research and Review (IJSR) ISSN NO: 2279-543X, Volume 8, Issue 5, May 2019, pp-650-
    654 (UGC Approved).
  • Sujaya H S, Suchit Shavi, Rohith J Bharadwaj, Yasha Jyothi M Shirur “Anger Detection Module for Assisting Dementia Patients”got published in International Journal of Innovative Research in Science, Engineering and Technology. (IJIRSET) Vol. 7 Issue: 6 July 2018 with ISSN (Online): 2319-8753 and Cross ref – DOI:10.15680/IJIRSET.2018.0706091 & impact Factor 7.08
  • July 2017 – June 2018
  • Yasha Jyothi M Shirur“Wireless Local Area Network Frame Classification to Access Categories based on User Priority” got published in International Journal of Innovative Research in Science, Engineering and Technology. (IJIRSET) Vol. 7 Issue: 6 June 2018 with ISSN (Online): 2319-8753 and Cross ref – DOI:10.15680/IJIRSET.2018.0706091 & impact Factor 7.089.
  • Anu K L, Yasha Jyothi M Shirur, and Mr. Prasanna Kumar Y “Design and Implementation of Driver Assistance System (Das) Using Raspberry Pi to Enhance Driver Safety”in International Journal of Engineering Research & Technology (IJERT) Vol. 5 Issue: 04 April 2018 with ISSN: 2395-0056.
  • Amshu Vinayak. T, Yasha Jyothi M Shirur “Automatic Control for Greenhouse Farming”got published in International Journal of Engineering Research & Technology (IJERT) Vol. 6 Issue: 09 September 2017 with ISSN: 2278-0181 and Cross ref – DOI Prefix: 10.17577.
  • Kritika M Sharma Aishwarya A,Yasha Jyothi M Shirur “Power Efficient Destination Address Generator of Direct Memory Access Controller in Multiprocessor SoC” got published in International Journal of Innovative Research in Computer and Communication Engineering (IJIRCCE) Vol. 5, Issue: 7 July 2017 with ISSN:2320-9801 and impact factor 6.577.
  • Akhila K Karuna N Kavya C,Yasha Jyothi M Shirur “Design and implementation of Power Efficient Linear Feedback Shift Register for BIST using Verilog” got published in International Journal of Innovative Research in Computer and Communication Engineering (IJIRCCE) Vol. 5, Issue: 7 July 2017 with ISSN:2320-9801 and impact factor 6.577.
  • July 2013 – June 2017
  • Sagar R, Yasha Jyothi M Shirur “Efficient Trash Management System Using Smart Bin”got published in International Research Journal of Engineering and Technology (IRJET) Vol. 4, Issue: 5 May 2017 with ISSN: 2395-0056 and impact factor 5.181.
  • K Shreshta Subodh Shetty, Yasha Jyothi M Shirur “Video Oculographic System enabling Communication for Patients suffering from Motor Neuron Disease”got published in Perspective in Communication, Embedded-Systems and Signal-Processing Vol. 1, Issue 2-05-2017 p-p19-21.
  • Nikitha Teggi, Yasha Jyothi M Shirur, Vishweshwar Mundkur“Modeling of LORA Transceiver in MATLAB using SIMULINK” IJMER Vol. 3, No. 6, 166-171, 159-162 with impact factor 3.518.
  • Yasha Jyothi M Shirur,Veena S Chakarvarthi, “Design and Implementation of Power efficient Micor Pipelined GALS based 2D FFT Processor Core”got published in  International Journal of Signal Processing Systems  Vol. 3, No. 2, p-p. 166-171, December 2015. DOI: 10.12720/ijsps.3.2.166-171 (IJSPS, ISSN:2315-4535;DOI: 10.12720/ijsps.
  • Ranjith Kumar M, Yasha Jyothi M Shirur, Ramudu B “Development of Verification Environment to Verify CSR Registers for DDR4 Memory Controller through APB Interface Using UVM Methodology”, ISSN 2394-3785  Available online at www.ijartet.com International Journal of Advanced Research Trends in Engineering and Technology (IJARTET) Vol. II, Special Issue XXVII, June 2015 in association with Dayananda Sagar College Of Engineering, National Conference On “Emerging Trends In VLSI, Embedded System, Nano Electronics And Telecommunication System” DSCE NCEVENT’15 JUNE 16 & 17,2015 58_62 All Rights Reserved © 2015 IJARTET.
  • Yasha Jyothi M Shirur, Lakshmi H R, Varchaswini R “Implementation of FSM-MBIST and Design of Hybrid MBIST for memory cluster in Asynchronous SoC”. This paper got published in International Journal of Computer Applications Technology and Research IJCAT- Volume 3– Issue 4, 216 – 220, 2014.
  • Nishanti G, Yasha Jyothi M Shirur, Ramudu B “Functional coverage for low power DDR2 Memory Controller in UVM”. This paper got published in International Journal of Computer Applications Technology and Research IJCAT- Volume 3– Issue 5, 292 – 295, 2014.
  • Yasha Jyothi M Shirur, Veena S Chakarvarthi, Kavana Hegde “Applying Shannon expansion concept for power optimization of digital design”. This paper got published in International Journal of Current Engineering and Technology (IJCET)-2013.

National Journals: 4

  • Nishanti G, Yasha Jyothi M Shirur, Ramudu B “Coverage driven verification environment development of low power ddr2 memory controller” Published in National Conference proceedings on VLSI, Image processing and Networking, Indira Institute of Technology, Chennai. 22-27 held on 28thof April 2014.
  • Kumarswamy, Yasha Jyothi M Shirur, Veena S Chakarvarthi “Implementation of Logic BIST for any Digital Core” presented in National Conference onRecent Advances in Electronics and Communication Engineering conducted during May 2013.
  • Sindhu, Yasha Jyothi M Shirur “Implementation of all digital phase locked loop with input fault detection” presented in National Conference onRecent Advances in Electronics and Communication Engineering conducted during May 2013.
  • Dharmendra N Kerur, Yasha Jyothi M Shirur, S.B. BhanuPrashanth “Design of mixed signal CMOS-PLLwith improved acquisition and its application as frequency synthesizer” presented in National Conference on Recent Trends in Industrial Electronics and Instrumentation CRTIEAI-2013 conducted during 7th June 2013.

 National/International Conference Proceedings:  19

 July 2020 – June 2021:

  • Madhuri R A, Mahima M Hampali, Nisarga Umesh, Pooja K S , Yasha Jyothi M. Shirur, Dr.Veena S. Chakravarthi “Design and Implementation of EDMA Controller for AI Based DSPSoCs for Real-Time Multimedia Processing” presented in 4th International Conference on ISMAC (IoT in Social, Mobile, Analytics and Cloud) organized by SCAD Institute of Technology at Palladam, India on 7th to 9th, October 2020, got published in IEEE Xplore Digital Library. (Scopus Indexed)
  • Bharathi, Dr. Yasha Jyothi M Shirur, P. L. Lahari “Performance evaluation of Distributed Arithmetic based MAC Structures for DSP Applications”Presented in 7th International Virtual Conference on Smart Structures and Systems (ICSSS 2020) organized by Saveetha Engineering College, Chennai. Tamil Nadu, India on 23rd and 24th of July 2020, got published in IEEE Xplore Digital Library. (Scopus Indexed).
  • L. Lahari, M. Bharathi, Dr. Yasha Jyothi M Shirur “High Speed Floating Point Multiply Accumulate Unit Using Offset Binary Coding”Presented in 7th International Virtual Conference on Smart Structures and Systems (ICSSS 2020) organized by Saveetha Engineering College, Chennai. Tamil Nadu, India on 23rd and 24th of July 2020, got published in IEEE Xplore Digital Library. (Scopus Indexed).

July 2019-June 2020:

  • L. Lahari,  M. Bharathi,  Yasha Jyothi M Shirur, “An efficient Truncated MAC using Approximate Adders for Image and Video Processing Applications”Presented in the 4th International Conference in Electronics and Informatics (ICOEI 20220) organized by SCAD college of Engineering and Technology, Tamil Nadu, India during 15-17, June 2020 got published in IEEE Xplore Digital Library. (Scopus Indexed)
  • Yasha Jyothi M Shirur, M. Bharathi “Optimized Synthesis of Dadda Multiplier Using Parallel Prefix Adders”presented in the 2nd IEEE International Conference on smart System and Inventive Technology ICSSIT 2019 organized by Francis Xavier Engineering College during 27-29 November 2019 at Tirunelveli India, got published in IEEE Xplore Digital Library, 978-1-7821-5517-2 (Scopus Indexed)

July 2018 – June 2019:

  • Yasha Jyothi M Shirur, Kritika M Sharma, Aishwarya A“Design and implementation of

Efficient Direct Memory Access (DMA) Controller in Multiprocessor SoC” presented International Conference on Networking Embedded and Wireless System (ICNEWS-2018) held on 27th and 28th of December 2018 and got published in IEEE Xplore Digital Library. 978- 1-5386-7949-4/18/2018 (Scopus Indexed).

  • Akhila K, Karuna N and Yasha Jyothi M Shirur “Design and Implementation of Power

Efficient Logic BIST With High Fault Coverage Using Verilog” presented in International Conference on Networking Embedded and Wireless System (ICNEWS-2018) held on 27th and 28th of December 2018 and got published in IEEE Xplore Digital Library. 978-1-5386-7949-4/18/2018 (Scopus Indexed).

  • Yasha Jyothi M Shirur Ujwal S S, Sana Anaum, Suhas N Bhargav Zeeshan Saquib “Blinkom: A Smart Solution for the MND Patients”in 3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT-2018), MAY 2018.

July 2011 – June 2018

    • Chaitrashree K, Yasha Jyothi M Shirur,Vishweshwar Mundkur “SIMULINK Modeling of blood pressure system” got published in Proceedings of 26th IRF International Conference PP-9-12 ISBN: 978-93-86083-38-8. International Conference on Engineering and Technology held on 12th June 2016.
    • Swathi S, Ramya Jagadish, Pankaja K, Yasha Jyothi M Shirur “Fault Tolerant carry select Adder and Dadda Multiplier using Reversible Logic Technique”got published Conference Proceedings with ISBN: 978-81-92958-06-1. International Conference on Emerging Trends in Engineering and Technology [IFERP] held on 22nd May 2016.
    • Yasha Jyothi M Shirur, Shurthi S “Implementation of IEEE 1687 standard for Access Instrumentation using Verilog”presented in International Conference on Signal Processing, Communication and Computational Research got published in Institute of Engineering Research & Publication IFERP Proceedings, May 18th and 19th 2016.
    • Yasha Jyothi M Shirur, Chetana Bilure, Veena S Chakravarthi“Performance analysis of low power microcode based asynchronous P-MBIST” Presented in 4th International conference on Advances in computing, communications & Informatics. (ICACC-2015) conducted during 10-13th August in Aluva Kochi, India and got published in IEEE Xplore Digital Library. P-P 555-560   DOI: 1109/ICACCI.2015.7275667, ISBN: 978-1-4799-8792-4/15 with impact factor 5.629.
    • Yasha Jyothi M Shirur, Suhasin Hegde, Vindhya Adiga, Rakshith G R and Priyanka S Bhat IEEE Standard 1149.1 Boundary Scan Insertion Methodology for Power Efficient Asynchronous 8 bit Processor Core” presented in International Conference on VLSI and Signal Processing and got published in ICVSP-2014 Proceedings , August 13thand 14th 2014.
    • Yasha Jyothi M Shirur, Veena S Chakarvarthi, Lakshmi H RImplementation of Area Efficient Hybrid MBIST for Memory clusters in Asynchronous SoC” Presented in Fifth International Symposium on Electronic System Design (ISED- 2014) conducted during 15-17 December 2014 in Surathkal, Mangalore, India and got published in IEEE Computer Society. P-P 226 – 227 DOI:1109/ISED.2014.57.
    • Yasha Jyothi M Shirur Mrs. Rekha P “Towards A Hybrid Pan sharpening Algorithm For High  Resolution Satellite Imagery” Presented in Fourth International Conference of Communication and Signal Processing (ICCSP-2015) conducted during 2-4thApril 2015 in Melmaruvathur, Tamilnadu, India and got published in IEEE Xplore Digital Library P-P 1252 – 1256 DOI:1109/ICCSP.2015.7322708.
    • Yasha Jyothi M Shirur, Veena S Chakarvarthi, Varchaswini R “Adder based Address generator for Embedded Memories”presented in International Conference of VLSI, Communication, Advanced Devices, Signals & Systems and Networking (VCASAN-2013). This paper got published in lecture Notes in Electrical Engineering 258 Springer Proceedings.
    • Dharmendra N Kerur, Yasha Jyothi M Shirur, S.B Bhanu Prashanth “Design of 1GHz Mixed Signal CMOS-PLL with Fast Phase and Frequency Acquisition” presented in International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking (VCASAN-2013) conducted during 17-19 July 2013. This paper got published in VCASAN-2013 Proceedings.
    • Yasha Jyothi M Shirur, Veena S Chakravarthi, Gourav Thakur, “Performance Analysis of 8-bit pipelined Asynchronous Processor Core”presented in an IP-SoC-2013, Grenoble, France.
    • Shiva Kumar K, Yasha Jyothi M Shirur, Veena S Chakravarthi, “Reliable Boundary Scan Insertion Methodology for Multi-Chip Module Based Designs” presented in International Conference on VLSI and Signal published in ICVSP-2012 Proceeding, May 4-5th 2012, pp.113-
      118.

Book

  • Proceeding of International conference on VLSI Communication, Advanced Devices, Signal & Systems and Networking (VCASAN-2013) held at BNMIT during July 17-18, 2013.

Hobbies

Sports 

Music

Any other things

  • Faculty Development Program Convenerfor “Digital Design Flow Using Xilinx and MATLAB Tolls for Image Processing Applications” held during 20th to 24th January 2020.
  • Faculty Development Program Convenerfor “IoT base Project design and Development” held during 24th to 29th June 2019
  • Chief Test Coordinator, BNMIT (2017-2018).
  • Member,Anti ragging Squad, BNMIT (2017-18).
  • Coordinator, TATVA, BNMIT (2016-2017).
  • Technical session coordinatorfor International Conference on Fluid Dynamic and its Applications (ICFD-2017) conducted by mathematics department from July 12-14, 2017.
  • Pre-Conference Tutorial Coordinatorfor International Conference on Power and Advanced Control Engineering ICPACE-2015.
  • Coordinator for International Conference of VLSI, Communication, Advanced Devices, Signals & Systems and Networking (VCASAN-2013)conducted by ECE & TCE in the year 2013.