University Level

1. Board of Examiners: Member, VTU, Belgaum (2021-2022)
2. Doctoral Committee member in VTU affiliated colleges
3. Evaluated 2 Ph.D. Thesis of reputed universities in India.
4. Institute Level Final Year Project Committee Coordinator (IPCC), VTU, 18 June 2021.
5. Deputy Chief Superintendent (External) at BMSCE, Bangalore for the conduction of January 2012 B.E. examinations of VTU, Belgaum.
6. Deputy Chief Superintendent (External) at DSCE, Bangalore from 17-07-2017 to 2-08-2017 for the conduction of June 2017 B.E. examinations of VTU, Belgaum.

College Level

1. Squad Team Member: Autonomous Semester End Examination (2021-2022)
2. Organizer for 3 Days Workshop on Design and Implementation of Humanoid Robotics organized from BNMIT under ISTE Students Chapter-BNMIT from 7-4-2022 to 9-4-2022.
3. Academic Council Member for Autonomous (2021-2022)
4. Member Secretary: Joint Board of Studies (2021-2022)
5. Ladies Hostel Supervisor: (2021-2022)
6. Member, Anti ragging Squad, BNMIT (2021-2022)
7. Chief Test Coordinator, BNMIT (2017-2018).
8. Member, Anti ragging Squad, BNMIT (2017-18).
9. Coordinator, TATVA, BNMIT (2016-2017).
10. Technical session coordinator for International Conference on Fluid Dynamic and its Applications (ICFD-2017) conducted by mathematics department from July 12-14, 2017.
11. Pre-Conference Tutorial Coordinator for International Conference on Power and Advanced Control Engineering ICPACE-2015.
12. Coordinator for International Conference of VLSI, Communication, Advanced Devices, Signals & Systems and Networking (VCASAN-2013) conducted by ECE & TCE in the year 2013.
13. Editor for the proceeding of international conference on VLSI Communication, Advanced Devices, Signal & Systems and Networking (VCASAN-2013) held at BNMIT during July 17-18, 2013.

Department Level

1. PG Coordinator for VLSI Design and Embedded System, Dept of ECE, BNMIT (2016-till date).
2. Member Secretary: ECE Board of Studies (2021-2022)
3. PAAC and DAB Member
4. Counselor for 8th Semester
5. Organizer for 2 Days webinar series on Stay Fit and Stay Safe organized from department of ECE under ISTE Students Chapter- BNMIT on 18-6-2021 and 19-6-2021.
6. Skill Development Program Coordinator (2019-2020
7. Faculty Development Program Convener for “Digital Design Flow Using Xilinx and MATLAB Tolls for Image Processing Applications” held during 20th to 24th January 2020.
8. Faculty Development Program Convener for “IoT base Project design and Development” held during 24th to 29th June 2019.

Awards and Achievements

1. Received “Senior Membership” as a reorganization from Professional body IEEE Advancing Technology for Humanity in the year 2022.
2. Received appreciation letters from BNMIT Management for having scored greater than 90% in staff appraisal evaluation during 2018-19 and Received Rs. 5000/- cash award along with appreciation letter for 2019-2020. Received Rs. 10,000/- cash award along with the appreciation letter for 2020-21.
3. Received “Outstanding Scientist Award”, in the International Scientist Awards on Engineering, Science and Medicine, held on 06 & 07-Mar-2021, Goa, India, Organized by VDGOOD Professional Association.
4. Best Paper Award for the paper“ Performance evaluation of Distributed Arithmetic based MAC Structures for DSP Applications” in 7^th International Virtual Conference on Smart Structures and Systems (ICSSS 2020) organized by Saveetha Engineering College, Chennai. Tamil Nadu, India on 23^rd and 24^th of July 2020.
5. Best Paper-Fourth Prize for the paper “Low Power High Speed Vedic Techniques in Recent VLSI Design – A Survey” in 1^stAll India Paper writing competition on Emerging Research (PACER) 2020, organized by WorldServe Online held in July 2020.
6. Merit Awardreceived while pursuing M. Tech in 2003 at BMSCE, Bangalore.
7. Best Oral Presenter Awardfor Best Presentation in International Conference of Communication and Signal Processing (ICCSP-2014), Bangkok, Thailand

Internship/SDP Conducted

1. Under Skillbot company conducted 6 weeks internship on Project based Digital design Modelling using Verilog for PG students from 17-8-2020 to 26-9-2020.
2. Conducted 50 hours (10 days – 5 hours per day) Skill development program on “Digital Design Modelling Using Verilog HDL” from 27-7-2020 to 8-8-2020.

Invited Talks

1. “Tips for Effective Paper Writing” in a one week Online National Level Development Programme (FDP) on Essential for Research organized by Dr. D. Y. Patil Institute of Technology, Pimpri, Pune on 21-4-2022.
2. Book Review on: “A Practical Approach to VLSI System on Chip (SoC) Design” under Webinar Series on Nanotechnolgy organised by IEEE-BNMIT in association with Nanotechnology Council on 19-11-2020.
3. “Research and Professional Development” organized on Faculty Induction Program from 22nd & 23rd September 2020.
4. “Online Education- Pros and Cons” Organized by IEEE BNMIT Student Branch in association With IEEE Nanotechnology Council, Bengaluru on 1-6-2020.

Editorial/Technical/Reviewer

1. PhD Thesis Evaluator for Pune University for the Thesis with the title Design & Development of UWB Wearable Antenna for Wireless Applications submitted by MS. Mugdha Anand Kango.
2. PhD Thesis Evaluator for Bharathi Deemed University Encryption of Features Generated by Fusion of Face, Palm Vein and Fingerprint Biometrics for Futuristic Security Applications. By MS. PRITI. SHENDE.
3. Reviewer: ISA Transactions “The Journal of Automation”, an Elsevier Journal 2021.
4. Reviewer: Indian Journal of Science & Technology (IJST) 2021-1846.
5. Technical Committee Member: 9th International Conference on Electronics Engineering and Technology (ICEET 2022) will be held in Tianjin, China during July 1-3, 2022.
6. Reviewer: ISA Transactions Elsevier Journal (ISATRANS-D-21-02554)- 2021-222020-21
7. Reviewer: 5th International Conference on Electrical, Electronics, Communication, Computer Technologies, and Optimization Techniques (ICEECCOT-2021). 10-11, December 2021, Mysuru, Karnataka, INDIA.
8. National Advisory Committee: International Conference on Recent Challenges in Engineering Science and Technology (ICRCEST 2021) – Virtual Conference 27th – 28th August 2021 Organized by Institute for Engineering Research and Publication (IFERP).
9. National Advisory Committee Member: 2nd International Conference on Futuristic Trends in Embedded Systems and Networking (ICFTEN 2021) – Virtual Conference in association with Institute for Engineering Research and Publication (IFERP). 20th -21sr May 2021, Rao Bahadur Y Mahabaleshwarappa Engineering College, Balarri.
10. International Journal of Engineering Research & Technology (IJERT)
11. Technical Committee: International Conference on Computer and Communications ICCC-IEEE on December 06-09, 2019 in Chengdu, China.

Session Chair/ Judge

1. Judge for Mock Paper Presentation organized by IEEE-BNMIT Student Branch in association with IEEE Nanotech Council on 17th October 2020.

Expertise/Subjects handled

UG

• Wireless and Cellular Communication
• Basic Electronics
• Analog electronics
• Digital Electronics
• Network Analysis
• Linear Integrated circuits and applications
• Digital design using Verilog Transmission lines and Wave Guides
• Information Theory and Coding
• VLSI Design
• Principles of Communication Systems Digital Communication
• Programming with C++
• Cryptography and Network Security

PG

• Digital VLSI Design
• Analog Mixed mode VLSI Design
• High Speed VLSI Design
• VLSI Testing and Testability
• VLSI Technology
• Advanced VLSI design
• Low Power VLSI design
• Testing of VLSI circuits
• SoC Design
• ASIC Design
• VLSI System Design

Research Interest:

• VLSI Design
• Design for Testability
• Low Power VLSI Design
• Embedded Systems
• Antenna Design for Inter and Intra chip communication, Microstrip Antenna Design, Image processing, Pattern Recognition, Digital Signal Processing, Designed A-SoC (Zeus A-SoC) consisting of A-RISC Processor Core, A-DSP Processor Core, 2-D FFT Engine, defined test techniques for A-SoC, filed patent on Asynchronous System on Chip Test through JTAG: Testing of asynchronous blocks with handshake pipelines (protocol) in A-SoC, through JTAG is proposed and implemented. Inserting asynchronous JTAG test logic speeds up the test process is functionally verified.
• Present Research Students = 2 (Mrs. Bharathi M and Poornima R are pursuing Ph.D in Dept of ECE, BNMIT, under VTU, Belagavi).
• Reviewer for Elsevier, Springer and Scopus indexed Journal. Technical Committee member and reviewer for international conferences.

Patent Filed:

a. Patent Filed with Patent no. 202141020972.

Title: “Design of VLSI System to detect abnormal behavior of Heartbeat”

Inventors: Dr. Yasha Jyothi M Shirur, Dr. N. V. Uma Reddy and Dr. Manju Devi.

Date of Filing: 09/05/2021

Date of Publication: 25/06/2021

b. Patent filed with patent no: 202041057157.

Title: “System, Method and tool for circuit design and Implementation”

Faculty Inventors: Dr. Veena S Chakravarthi, Dr. Yasha Jyothi M Shirur

Student Inventors: Sowndarya S, Shubham Raj, Vismith Upadhya P J

Date of Filing: 30-12-2020

c. Patent filed with patent no: 201641022110.

Title: “Method, System and Apparatus for Asynchronous SoC Testing and Validation”

Inventors: Yasha Jyothi M Shirur, Dr. M. S. Suresh, Dr. Veena S Chakravarthi.

Date of Filing: 28-06-2016.

Date of Publication: 26-01-2018.

Date of Examination: 13-08-2019

Funding received

Nil

Publications: 45

International Journals: 27

• July 2021 – June 2022:
• Bharathi. M and Yasha Jyothi M Shirur “Power-Efficient Modulo Multiply and Accumulate Unit Using Distributed Arithmetic” got published in Design Engineering Journal with ISSN: 0011-9342 | Year 2021 Issue: 9 | Pages: 3548 – 3556. Scopus Indexed (Q4 Rated Journal) Scopus ID: https://www.scopus.com/sourceid/28687. Journal website: http://www.thedesignengineering.com/index.php/DE
• Sowmya S and Yasha Jyothi M Shirur “Smart IOT Enabled Power Theft Detection and Transformer Health Monitoring System” got published in Bulletin Monumental Journal , Vol. 22, Issue No. 2021, ISSN / e-ISSN 0007-473X, p-p 79-91, Publisher: Soc Fr Archeologie Musee Monument Francais , Palais De Chaillot Aile De Paris, Paris, France, 75016, http://bulletinmonumental.com/gallery/10-july2021.pdf , Web of Science.
• July 2020 -June 2021:
• Bharathi. M and Yasha Jyothi M Shirur “ VLSI Implementation Of Multiply And Accumulate Unit Using Offset Binary Coding Distributed Arithmetic” got published in Turkish Journal of Computer and Mathematics Education, Vol. 12 No. 11 (2021), E-ISSN: 1309-4653, p-p 4739-4749, publisher Karadeniz Technical University, https://www.turcomat.org/index.php /turkbilmat/article/view/6647 , Scopus Indexed.(Q4)
• Bharathi. M and Yasha Jyothi M Shirur “Floating-Point Multiply and Accumulate Unit Core using Distributed Arithmetic for DSP Applications” got published in Turkish Journal of Computer and Mathematics Education, Vol. 12 No. 11 (2021), E-ISSN: 1309-4653, p-p 4730 – 4738, publisher Karadeniz Technical University, https://www.turcomat.org/index.php/ turkbilmat/article/view/6646 Scopus Indexed.(Q4)
• Rajyalakshmi Chikkani, Bharathi. M and Yasha Jyothi M Shirur “VLSI Implementation of Multiply and Accumulate Unit Using Distributed Arithmetic” got published in Bioscience Biotechnology Research Communications Special Issue Vol. 13 No. 15, Print ISSN: 0974-6455 Online ISSN: 2321-4007, Doi: http://dx.doi.org/10.21786/bbrc/13.15/37, impact factor 7.728. Journal is listed in Emerging Sources Citation Index (ESCI) / Web of Science (WoS), NAAS Score 4.31.
• July 2020 – June 2021:
• Muskan Tated, Sri Haripriya Rai N, Bindu S, Yasha Jyoti M Shirur “Nano Electronics and it’s Wide Applications” got published in GIS Science Journal with ISSN No: 1869-9391; VOLUME 7, ISSUE 12, Dec 2020, PP 436-445, Impact factor: 6.1 (Scopus Indexed Journal).
• Sahil, Soumita Paul, Yasha Jyothi M Shirur “Power Optimization Techniques adopted at various abstraction levels in system on Chip Design- A Survey” got published in International Journal for Research in Applied Science & Engineering Technology (IJRASET) ISSN:2321-9653; IC value:45.98, SJ Impact factor:7.429 (Volume 8 Issue X) Oct 2020.
• Deepa S. Yasha Jyothi M Shirur “Design of flexible FFT core for fast computing of digital signals in real time applications”got published in International Journal of Advance Research, Ideas and Innovations in Technology (IJARIIT) ISSN: 2454-132X Impact factor: 6.078 (Volume 6, Issue 4) pp 127-131 July 2020.
• Swathi Dayananda, Varshitha K. R, Rohini T, Yasha Jyothi M Shirur, Jyothi Munavalli, “Low Power High Speed Vedic Techniques in Recent VLSI Design – A Survey” got published inPerspectives in Communication, Embedded-Systems and Signal-Processing (PiCES) – An International Journal with ISSN: 2566-932X. PP 34-43. July 2020.
• July 2019-June 2020:
• L. Lahari, M. Bharathi, Yasha Jyothi M Shirur“A Review on Distributed Arithmetic and Offset Binary Coding” got published in i-manager’s Journal on Digital Signal Processing, Vol. 7 No. 3lJuly – September 2019 PP 27-34.
• Anshu Kumar, Nisarga U, Yasha Jyothi M Shirur “Design and Development of Beach Sand Cleansing Equipment Based on Electro-Hydraulic Mechanism”got published in International Journal of Advanced Science and Technology (IJAST), ISSN No. 2005-4238 Volume 29 No. 12 PP 163-170 (Scopus Indexed).
•  July 2018 – June 2019:
• Yasha Jyothi M Shirur “Efficient Method to Measure Dynamic Temperature Variations in a Non-Uniform Heat Dissipated Integrated Chip”got published in International Journal of Computer Sciences and Engineering. (IJCSE) Vol.-7, Issue-6, June 2019 (UGC Approved).
• Yasha Jyothi M Shirur, Harshitha A “An Efficient Radix-3 Multiplier less 2D Convolution Filter for Visual Search Applications”got published in International Journal of Scientific Research and Review (IJSR) ISSN NO: 2279-543X, Volume 8, Issue 5, May 2019, pp-650-
  654 (UGC Approved).
• Sujaya H S, Suchit Shavi, Rohith J Bharadwaj, Yasha Jyothi M Shirur “Anger Detection Module for Assisting Dementia Patients”got published in International Journal of Innovative Research in Science, Engineering and Technology. (IJIRSET) Vol. 7 Issue: 6 July 2018 with ISSN (Online): 2319-8753 and Cross ref – DOI:10.15680/IJIRSET.2018.0706091 & impact Factor 7.08
• July 2017 – June 2018
• Yasha Jyothi M Shirur“Wireless Local Area Network Frame Classification to Access Categories based on User Priority” got published in International Journal of Innovative Research in Science, Engineering and Technology. (IJIRSET) Vol. 7 Issue: 6 June 2018 with ISSN (Online): 2319-8753 and Cross ref – DOI:10.15680/IJIRSET.2018.0706091 & impact Factor 7.089.
• Anu K L, Yasha Jyothi M Shirur, and Mr. Prasanna Kumar Y “Design and Implementation of Driver Assistance System (Das) Using Raspberry Pi to Enhance Driver Safety”in International Journal of Engineering Research & Technology (IJERT) Vol. 5 Issue: 04 April 2018 with ISSN: 2395-0056.
• Amshu Vinayak. T, Yasha Jyothi M Shirur “Automatic Control for Greenhouse Farming”got published in International Journal of Engineering Research & Technology (IJERT) Vol. 6 Issue: 09 September 2017 with ISSN: 2278-0181 and Cross ref – DOI Prefix: 10.17577.
• Kritika M Sharma Aishwarya A,Yasha Jyothi M Shirur “Power Efficient Destination Address Generator of Direct Memory Access Controller in Multiprocessor SoC” got published in International Journal of Innovative Research in Computer and Communication Engineering (IJIRCCE) Vol. 5, Issue: 7 July 2017 with ISSN:2320-9801 and impact factor 6.577.
• Akhila K Karuna N Kavya C,Yasha Jyothi M Shirur “Design and implementation of Power Efficient Linear Feedback Shift Register for BIST using Verilog” got published in International Journal of Innovative Research in Computer and Communication Engineering (IJIRCCE) Vol. 5, Issue: 7 July 2017 with ISSN:2320-9801 and impact factor 6.577.
• July 2013 – June 2017
• Sagar R, Yasha Jyothi M Shirur “Efficient Trash Management System Using Smart Bin”got published in International Research Journal of Engineering and Technology (IRJET) Vol. 4, Issue: 5 May 2017 with ISSN: 2395-0056 and impact factor 5.181.
• K Shreshta Subodh Shetty, Yasha Jyothi M Shirur “Video Oculographic System enabling Communication for Patients suffering from Motor Neuron Disease”got published in Perspective in Communication, Embedded-Systems and Signal-Processing Vol. 1, Issue 2-05-2017 p-p19-21.
• Nikitha Teggi, Yasha Jyothi M Shirur, Vishweshwar Mundkur“Modeling of LORA Transceiver in MATLAB using SIMULINK” IJMER Vol. 3, No. 6, 166-171, 159-162 with impact factor 3.518.
• Yasha Jyothi M Shirur,Veena S Chakarvarthi, “Design and Implementation of Power efficient Micor Pipelined GALS based 2D FFT Processor Core”got published in  International Journal of Signal Processing Systems  Vol. 3, No. 2, p-p. 166-171, December 2015. DOI: 10.12720/ijsps.3.2.166-171 (IJSPS, ISSN:2315-4535;DOI: 10.12720/ijsps.
• Ranjith Kumar M, Yasha Jyothi M Shirur, Ramudu B “Development of Verification Environment to Verify CSR Registers for DDR4 Memory Controller through APB Interface Using UVM Methodology”, ISSN 2394-3785  Available online at www.ijartet.com International Journal of Advanced Research Trends in Engineering and Technology (IJARTET) Vol. II, Special Issue XXVII, June 2015 in association with Dayananda Sagar College Of Engineering, National Conference On “Emerging Trends In VLSI, Embedded System, Nano Electronics And Telecommunication System” DSCE NCEVENT’15 JUNE 16 & 17,2015 58_62 All Rights Reserved © 2015 IJARTET.
• Yasha Jyothi M Shirur, Lakshmi H R, Varchaswini R “Implementation of FSM-MBIST and Design of Hybrid MBIST for memory cluster in Asynchronous SoC”. This paper got published in International Journal of Computer Applications Technology and Research IJCAT- Volume 3– Issue 4, 216 – 220, 2014.
• Nishanti G, Yasha Jyothi M Shirur, Ramudu B “Functional coverage for low power DDR2 Memory Controller in UVM”. This paper got published in International Journal of Computer Applications Technology and Research IJCAT- Volume 3– Issue 5, 292 – 295, 2014.
• Yasha Jyothi M Shirur, Veena S Chakarvarthi, Kavana Hegde “Applying Shannon expansion concept for power optimization of digital design”. This paper got published in International Journal of Current Engineering and Technology (IJCET)-2013.

National Journals: 4

• Nishanti G, Yasha Jyothi M Shirur, Ramudu B “Coverage driven verification environment development of low power ddr2 memory controller” Published in National Conference proceedings on VLSI, Image processing and Networking, Indira Institute of Technology, Chennai. 22-27 held on 28^thof April 2014.
• Kumarswamy, Yasha Jyothi M Shirur, Veena S Chakarvarthi “Implementation of Logic BIST for any Digital Core” presented in National Conference onRecent Advances in Electronics and Communication Engineering conducted during May 2013.
• Sindhu, Yasha Jyothi M Shirur “Implementation of all digital phase locked loop with input fault detection” presented in National Conference onRecent Advances in Electronics and Communication Engineering conducted during May 2013.
• Dharmendra N Kerur, Yasha Jyothi M Shirur, S.B. BhanuPrashanth “Design of mixed signal CMOS-PLLwith improved acquisition and its application as frequency synthesizer” presented in National Conference on Recent Trends in Industrial Electronics and Instrumentation CRTIEAI-2013 conducted during 7^th June 2013.

National/International Conference Proceedings:  21

July 2021 – June 2022:

• M Bharathi, Dr. Yasha Jyothi M Shirur “Area Efficient Multiply and Accumulate Core Design on FPGA using Pezari’s Multiplication” presented in National Conference on Industrial IoT and Automation (NCIITA) Organized by SRM Institute of Science and Technology during 5th-6th May 2022.
• M Bharathi, Dr. Yasha Jyothi M Shirur “FPGA Realization of High Speed Multiply and Accumulate Cores to Digital Signal Processing: Distributed Arithmetic and Offset Binary Coding” presented in national conference on Recent Trends in Engineering and Technology -2021 (RTET-2021) organized by department of Electrical and Electronics Engineering, KSRM College of Engineering (Autonomous) on 29-12-2021.

 July 2020 – June 2021:

• Madhuri R A, Mahima M Hampali, Nisarga Umesh, Pooja K S , Yasha Jyothi M. Shirur, Dr.Veena S. Chakravarthi “Design and Implementation of EDMA Controller for AI Based DSPSoCs for Real-Time Multimedia Processing” presented in 4th International Conference on ISMAC (IoT in Social, Mobile, Analytics and Cloud) organized by SCAD Institute of Technology at Palladam, India on 7th to 9th, October 2020, got published in IEEE Xplore Digital Library. (Scopus Indexed)
• Bharathi, Dr. Yasha Jyothi M Shirur, P. L. Lahari “Performance evaluation of Distributed Arithmetic based MAC Structures for DSP Applications”Presented in 7^th International Virtual Conference on Smart Structures and Systems (ICSSS 2020) organized by Saveetha Engineering College, Chennai. Tamil Nadu, India on 23^rd and 24^th of July 2020, got published in IEEE Xplore Digital Library. (Scopus Indexed).
• L. Lahari, M. Bharathi, Dr. Yasha Jyothi M Shirur “High Speed Floating Point Multiply Accumulate Unit Using Offset Binary Coding”Presented in 7^th International Virtual Conference on Smart Structures and Systems (ICSSS 2020) organized by Saveetha Engineering College, Chennai. Tamil Nadu, India on 23^rd and 24^th of July 2020, got published in IEEE Xplore Digital Library. (Scopus Indexed).

July 2019-June 2020:

• L. Lahari,  M. Bharathi,  Yasha Jyothi M Shirur, “An efficient Truncated MAC using Approximate Adders for Image and Video Processing Applications”Presented in the 4^th International Conference in Electronics and Informatics (ICOEI 20220) organized by SCAD college of Engineering and Technology, Tamil Nadu, India during 15-17, June 2020 got published in IEEE Xplore Digital Library. (Scopus Indexed)
• Yasha Jyothi M Shirur, M. Bharathi “Optimized Synthesis of Dadda Multiplier Using Parallel Prefix Adders”presented in the 2nd IEEE International Conference on smart System and Inventive Technology ICSSIT 2019 organized by Francis Xavier Engineering College during 27-29 November 2019 at Tirunelveli India, got published in IEEE Xplore Digital Library, 978-1-7821-5517-2 (Scopus Indexed)

July 2018 – June 2019:

• Yasha Jyothi M Shirur, Kritika M Sharma, Aishwarya A“Design and implementation of

Efficient Direct Memory Access (DMA) Controller in Multiprocessor SoC” presented International Conference on Networking Embedded and Wireless System (ICNEWS-2018) held on 27^th and 28^th of December 2018 and got published in IEEE Xplore Digital Library. 978- 1-5386-7949-4/18/2018 (Scopus Indexed).

• Akhila K, Karuna N and Yasha Jyothi M Shirur “Design and Implementation of Power

Efficient Logic BIST With High Fault Coverage Using Verilog” presented in International Conference on Networking Embedded and Wireless System (ICNEWS-2018) held on 27^th and 28^th of December 2018 and got published in IEEE Xplore Digital Library. 978-1-5386-7949-4/18/2018 (Scopus Indexed).

• Yasha Jyothi M Shirur Ujwal S S, Sana Anaum, Suhas N Bhargav Zeeshan Saquib “Blinkom: A Smart Solution for the MND Patients”in 3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT-2018), MAY 2018.

July 2011 – June 2018

• • Chaitrashree K, Yasha Jyothi M Shirur,Vishweshwar Mundkur “SIMULINK Modeling of blood pressure system” got published in Proceedings of 26^th IRF International Conference PP-9-12 ISBN: 978-93-86083-38-8. International Conference on Engineering and Technology held on 12^th June 2016.
  • Swathi S, Ramya Jagadish, Pankaja K, Yasha Jyothi M Shirur “Fault Tolerant carry select Adder and Dadda Multiplier using Reversible Logic Technique”got published Conference Proceedings with ISBN: 978-81-92958-06-1. International Conference on Emerging Trends in Engineering and Technology [IFERP] held on 22^nd May 2016.
  • Yasha Jyothi M Shirur, Shurthi S “Implementation of IEEE 1687 standard for Access Instrumentation using Verilog”presented in International Conference on Signal Processing, Communication and Computational Research got published in Institute of Engineering Research & Publication IFERP Proceedings, May 18^th and 19th 2016.
  • Yasha Jyothi M Shirur, Chetana Bilure, Veena S Chakravarthi“Performance analysis of low power microcode based asynchronous P-MBIST” Presented in 4^th International conference on Advances in computing, communications & Informatics. (ICACC-2015) conducted during 10-13^th August in Aluva Kochi, India and got published in IEEE Xplore Digital Library. P-P 555-560   DOI: 1109/ICACCI.2015.7275667, ISBN: 978-1-4799-8792-4/15 with impact factor 5.629.
  • Yasha Jyothi M Shirur, Suhasin Hegde, Vindhya Adiga, Rakshith G R and Priyanka S Bhat “IEEE Standard 1149.1 Boundary Scan Insertion Methodology for Power Efficient Asynchronous 8 bit Processor Core” presented in International Conference on VLSI and Signal Processing and got published in ICVSP-2014 Proceedings , August 13^thand 14th 2014.
  • Yasha Jyothi M Shirur, Veena S Chakarvarthi, Lakshmi H R“Implementation of Area Efficient Hybrid MBIST for Memory clusters in Asynchronous SoC” Presented in Fifth International Symposium on Electronic System Design (ISED- 2014) conducted during 15-17 December 2014 in Surathkal, Mangalore, India and got published in IEEE Computer Society. P-P 226 – 227 DOI:1109/ISED.2014.57.
  • Yasha Jyothi M Shirur Mrs. Rekha P “Towards A Hybrid Pan sharpening Algorithm For High  Resolution Satellite Imagery” Presented in Fourth International Conference of Communication and Signal Processing (ICCSP-2015) conducted during 2-4^thApril 2015 in Melmaruvathur, Tamilnadu, India and got published in IEEE Xplore Digital Library P-P 1252 – 1256 DOI:1109/ICCSP.2015.7322708.
  • Yasha Jyothi M Shirur, Veena S Chakarvarthi, Varchaswini R “Adder based Address generator for Embedded Memories”presented in International Conference of VLSI, Communication, Advanced Devices, Signals & Systems and Networking (VCASAN-2013). This paper got published in lecture Notes in Electrical Engineering 258 Springer Proceedings.
  • Dharmendra N Kerur, Yasha Jyothi M Shirur, S.B Bhanu Prashanth “Design of 1GHz Mixed Signal CMOS-PLL with Fast Phase and Frequency Acquisition” presented in International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking (VCASAN-2013) conducted during 17-19 July 2013. This paper got published in VCASAN-2013 Proceedings.
  • Yasha Jyothi M Shirur, Veena S Chakravarthi, Gourav Thakur, “Performance Analysis of 8-bit pipelined Asynchronous Processor Core”presented in an IP-SoC-2013, Grenoble, France.
  • Shiva Kumar K, Yasha Jyothi M Shirur, Veena S Chakravarthi, “Reliable Boundary Scan Insertion Methodology for Multi-Chip Module Based Designs” presented in International Conference on VLSI and Signal published in ICVSP-2012 Proceeding, May 4-5th 2012, pp.113-
    118.

Book

• Proceeding of International conference on VLSI Communication, Advanced Devices, Signal & Systems and Networking (VCASAN-2013) held at BNMIT during July 17-18, 2013.

Hobbies

• Travelling and Cleaning

Sports 

• Throw Ball, Shuttle Badminton, Exercise and Indoor Activities

Music

• Listening to Melodies songs (Hindi and Kannada)

Any other things

• Linkedin profile is used to manage Professional Activity and Interaction outside world.
• Faculty Development Program Convener for “Digital Design Flow Using Xilinx and MATLAB Tolls for Image Processing Applications” held during 20^th to 24^th January 2020.
• Faculty Development Program Convenerfor “IoT base Project design and Development” held during 24^th to 29^th June 2019
• Chief Test Coordinator, BNMIT (2017-2018).
• Member,Anti ragging Squad, BNMIT (2017-18).
• Coordinator, TATVA, BNMIT (2016-2017).
• Technical session coordinatorfor International Conference on Fluid Dynamic and its Applications (ICFD-2017) conducted by mathematics department from July 12-14, 2017.
• Pre-Conference Tutorial Coordinatorfor International Conference on Power and Advanced Control Engineering ICPACE-2015.
• Coordinator for International Conference of VLSI, Communication, Advanced Devices, Signals & Systems and Networking (VCASAN-2013)conducted by ECE & TCE in the year 2013.