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    This post was last updated on       July 9th, 2021

Prabhavathi P


Designation :Associate Professor

Area of specialization :VLSI Design

Date of Joining BNMIT : 1st July 2005

Nature of Association (Regular/Contractual/Adjunct) : Regular

E-mail Id :prabhavathip@bnmit.in 

No. of years of Experience : 27 Years and 5 Months

Teaching : 27 years 5 months

Qualification: M. Tech., M. Sc.(IT)

DegreeInstitutionMonth & Year of Passing
M.Tech.UTL Technologies Pvt. Ltd., VTU Extension PG Centre, VTUDecember 2011
M.Sc. (IT)Karnataka state Open UniversityMarch 2005
B.E.JNNCE, Shimoga, Mysore UniversityDecember 1988

Experience

  • Teaching – 27 years 5 months
Sl  NoDesignationInstitutionDuration
1Associate Professor, Department of ECE,Department of ECE, BNMIT, Bengalurusince July 2012
2Lecturer, Department of ECE,BNMIT, Bengaluru,since July 2005
3Lecturer & H o D, Department of ElectronicsThe National College, Basavanagudi, BengaluruDec. 1998 to June 2005
4LecturerSJR College for Women, Bengaluru, KarnatakaJuly 1994 to Nov.1998
5LecturerDVS Polytechnic, Shimoga, KarnatakaDec. 1989 to April 1990
6LecturerBIET, Davanagere, KarnatakaAug. 1989 to Nov. 1989

Awards and Achievements

  •  Coordinator, FDP on Physical Design Challenges in DSM node VLSI Systems – January 2017
  • Speaker for the session on SDC commands in Physical design in FDP on Physical Design Challenges in DSM node VLSI Systems – January 2017
  • Co Ordinator for Skill development program on VLSI-ASIC Logic Synthesis from from 6th February  To 26th April, 2019.
  • Invited talk at Acharya Institute of Technology on Physical Design Challenges in FDP on Physical design using Innovus – July 2019
  • Co Ordinator for Skill development program on SoC Based IoT System using Xilinx Vivado from 3rd to 12th February 2020
  • Coordinator and Resource person for FDP on Virtual labs in Physics from 3rd to 7th February 2021.

Expertise/Subjects handled

Under Graduate:
  • Analog Electronic Circuits,
  • Electronic Communication
  • Wireless Communication
  • Fundamentals of CMOS
  • HDLs
  • Microelectronics
  • Linear Integrated Circuits
  • DSP algorithms and Architecture
  • Digital system design using Verilog
Post Graduate:
  • ASIC Design
  • Analog VLSI Design
  • Low Power VLSI Design
  • RF CMOS Design
  • Analog and Mixed mode VLSI Design
  • Synthesis and Optimization of Digital circuits
  • CAD for VLSI Design

Research Interest:

  • Low Power VLSI Design Methodology
  • SoC Design  (Architectural description to PD design)
  • Mixed Signal Design

Research Projects Completed

Title: Design of load aware adaptive drive strength CMOS Standard cell libraryFunding Agency: VTU, Belgaum, Karnataka, INDIAAmount: 10 LakhsDuration: 03 years (July 2011 – July 2014)

  • Principal Investigator: Dr. Veena S. Chakravarthi
  • Co – Investigator: Prabhavathi P
  • Status: Completed

IP Design-

Nine different IP s (Protocol based and RTL proven) have been designed which can be fabricated or utilized in other designs.

Analog Design-

  • Compressive Sensing in 180 nm
  • Low Dropout Regulator in 90 nm and 45nm.
  • SAR based 7 bit ADC
  • K Delta 1 Sigma ADC( 8 bit) with 56 db SNR

Digital Design-

  • Design and verification of PCIe 3.0

Funding received

Nil

International Journals:

  • Prabhavathi P, K U Prasad Bhat, Anirudh V, Hrishikesh Ravish, K V Kumaraswamy, “Design and Verification of Peripheral Component Interconnect Express (PCIe) 3.0” published in International Research Journal of Engineering and Technology (IRJET) Volume 7, Issue 8, August 2020 https://www.irjet.net/volume7-issue8 S.No: 154
  • Rekha P, Prabhavathi P, Veena S. Murthy, Padmaja Jain “A Survey of Floral Aroma Sensors” published in International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 05 Issue: 07 | July 2018 www.irjet.net, p-ISSN: 2395-0072
  • Prabhavathi P, Nikhita V “Design of Low-Dropout Regulator” published In International Journal of Applied Research, Volume 1, Issue 7, Page no. 323-330, 2015
  • Prabhavathi P, Namratha N Petkar, “Implementation of 5 Bit Error Correcting BCH IP Core of Code length 255 on FPGA” Published in IJERM Volume 03 Issue 07 (July 2016)

 International/ National Conference Proceedings

  • P, Anirudh V, Prasad U Bhat, Hrishikesh Ravish, Kumarswamy K V, “ Design and Verification of PCIe 3.0” in IETE sponsored National Conference on Emerging trends in Engineering, Science and Technology, 2020 NCETEST, at RNSIT, Bengaluru, India – 17th June 2020. (Adjudged as Best paper)
  • Prabhavathi P, Amulya Rao, Vandana Rao, Rachana Ramkumar “Compressive sensing using 180 nm Technology” in 4th International Conference on recent trends in Electronics, Informatics, Communication and Technology -2019 (RTEICT) at SVCE, Bengaluru, India – 17th -18th May 2019. (Now published in IEEE proceedings 02/03/2020: DOI-10.1109/RTEICT46194.2019.9016913)
  • Prabhavathi P, Anirudh V, Prasad U Bhat, Hrishikesh Ravish, Kumarswamy K V, “ Design and Verification of PCIe 3.0” in IETE sponsored National Conference on Emerging trends in Engineering, Science and Technology, 2020 NCETEST, at RNSIT, Bengaluru, India – 17th June 2020.
  • Prabhavathi P, Amulya Rao, Vandana Rao, Rachana Ramkumar “Compressive sensing using 180 nm Technology” in 4th Internationa Conference on recent trends in Electronics, Informatics, Communication and Technology -2019 (RTEICT) at SVCE, Bengaluru, India – 17th -18th May 2019.
    (Now published in IEEE proceedings 02/03/2020: DOI-10.1109/RTEICT46194.2019.9016913)
  • Prabhavathi P, Anuragini K “IOT based lightning prediction system and measurement of different weather parameters” in International conference on Multimedia Processing, Communication and Information Technology MPCIJ 2019 at JNNCE, Shivamogga, Karnataka during 8 -9, June 2018.
  • Prabhavathi P, Asha S “Novel Communication Interface for IoT Applications” at 30TH INTERNATIONAL CONFERENCE ON VLSI DESIGN & 16TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS. 7th -11thJanuary 2017 Hyderabad, India.
  • Nagendra P. B, Prabhavathi P, Namratha N Petkar, “Implementation of 5 Bit Error Correcting BCH IP Core of Code length 255 on FPGA” in National Workshop on Cryptology NWC – 2016,11th -13th , Aug.2016, organized by Jawaharlal Nehru National College of Engineering Shivamogga, Karnataka
  • Prabhavathi P and Nikitha V “Design of Low- Dropout Regulator” published in International Journal of Applied Research, Volume 1, Issue 7, 2015, page no. 323 – 330.
  • Prabhavathi P, Mahesh N B, Subodh Kumar Panda “ Design of A 12-Bit Cyclic Vernier Ring Time-to-Digital Converter” at VCASAN -2013- International conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking, BNMIT, Bangalore, July 17-19, 2013
  • Manu B N, Prabhavathi P “Design and Implementation of AMBA ASB APB Bridge for ARM SOCs”, at Student Conference of VCASAN -2013- International conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking, BNMIT, Bangalore, July 17-19, 2013
  • Pournima P R, Prabhavathi P, “ Design of Rail-to-Rail op-amp in 90 nm CMOS ” at Student Conference of VCASAN -2013- International conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking, BNMIT, Bangalore, July 17-19, 2013
  • Shwetha H N, Prabhavathi P “7 bit, 200 KSPS SAR ADC with Ultra low energy DAC and Clocked Comparator” at National Conference NCCSC – 2012 at KSIT, Bangalore, August 6, 2012( Adjudged best paper & presentation).
  • Veena S K, Prabhavathi P “Low Latency Parallel Architecture DPLL”, at National Conference National conference on VLSI and Communication System( VCS), at BIT, Bangalore, 30 & 31st October 2012.
  • Ramya Rajan, Prabhavathi P , Dr. Veena S Chakravarthi, “Design of a 4 bit accumulator using new 45nm low leaky standard cells”, IP-SoC 2011 Conference, Grenoble, France, Dec 7-8, 2011.
  • Ramya Rajan, Prabhavathi P, Dr. Veena S Chakravarthi, “Study of effectiveness of circuit level leakage power optimization techniques in DSM CMOS cells” at Proceedings of the International conference on Energy & Electrical systems ICEES- 2011, Kualalumper, Malasia.
  • Prabhavathi P, Dr. S B Bhanu Prashanth, Premananda P “Modeling and Design of K Delta 1 Sigma ADC ” at NCSCV10, SDMCET, Dharwad, Aug 13th 2010.
  • Prabhavathi P, Dr. S B Bhanu Prashanth, Premananda P “Design of K Delta 1 Sigma ADC” at NEWS10, BMSCE, Bangalore-04, Aug 4th 2010.
  • Prabhavathi P, and Dr. Veena S. Chakravarthi “At speed scan test challenges and future scope of work – A Survey ”, National conference on Recent trends in Instrumentation, Communication and Microelectronics INCOMM – 10, April 9th and 10th 2010 at Shri Vaishnav Institute of Technology & Science, Indore(MP). (Adjudged best in faculty category).
  • Prabhavathi P, Dr. M. S. Suresh “Coding data for energy miser wireless sensor network for data acquisition systems”, Prabhavathi P; National level conference on “Modern Trends in Communication” Oct 15-16, 2008; Vemana Institute of Technology, Bangalore. (adjudged best in category).
  • Prabhavathi P “A Study of Substrate technology and survey of modeling techniques for substrate resistance extraction” Paper presented at the National Conference on Next Generation Networks at B N M Institute of Technology, Bangalore in March 2007.

Book

Nil

Hobbies

  • Blogger on Technical topics
  • Columnist on Science related topics in newspapers.

Sports 

Music

Any other things

  • Life member – Karnataka Rajya Vignyana Parishat
  • Life member – IEI
  • Life member, The Institution of Engineers(India) (IEI)

Any other things:

Conferences Attended

  •  VCASAN-2013, BNMIT, Bangalore 17-19 June 2013
  • VLSID 2013 At Pune, India on Fellowship from 7 th Jan to 9 th Jan 2013
  • VDAT 2014 at P S G Tech, Coimbatore on Fellowship from 16th to 18th July 2014
  • VLSID 2014 at IIT-B, Mumbai from 5th to 7th Jan 2014
  • VLSID 2017 at Hyderabad 5th– 7thJan 2017
  • SPCOM 2020 (online) at IIsc. Bengaluru 19th– 24th of July 2020
    Participation in Training courses/Seminars/Workshops
  • Attended FDP at NIT Calicut and “CMOS Design”(24th-30th June 2013).
  • Attended Didactic workshop on “ Electronics System Design , Manufacturing & Testing(ESDMT )” (27thJuly – 31st July 2015).
  • Attended FDP on “Micro and Nano Sensors for Health Monitoring” at MSRIT 6Bengaluru, from 6 th to 11th June 2016 (Supported by TEQIP –II and IEEE Sensor Council/Bangalore Section).
  • Attended FDP on “Computer and Wireless Networks” Department of ECE,BNMIT, heldbetween 11th to 16th July 2016.
  • Attended six days FDP on “Physical Design challenges in DSM Node VLSI systems”, 16th to 21stJanuary 2017at BNMIT, Bengaluru.
  • Attended FDP on “Artificial Intelligence and Machine Learning” by Cognizant in BNMIT, 20thand 21st June 2019.
  • Attended FDP on “IOT based Project Design and Development” from 24th to 29th June 2019 at Department of ECE, BNMIT, Bengaluru
  • Attended FDP through MOOC on “Synthesis of Digital systems – NPTEL – AICTE”
    from August –November 2019
  • Attended FDP on “VLSI Chip Design Hands-on using Open source EDA Tools” conducted by MNIT Jaipur in association with Electronics and ICT Academies from 16th – 20th December 2019 atPSG College of Technology, Coimbatore.
  • Attended FDP through MOOC on “VLSI Physical Design – NPTEL – AICTE” from January –April 2020
  • Attended FDP on “Machine learning and Deep Learning using Python” at RNSIT, Bengaluru from 30th Jan 2020 to 1st Feb 2020.