The Department of Electronics and Communication Engineering, BNMIT, in association with IEEE Circuits and Systems Society (CAS) and IEEE Nanotechnology Council, successfully conducted a Two-Day Workshop on Custom IC Design Flow on 17th and 18th July 2025. The workshop, led by Mr. Rakesh from Entuple, provided hands-on training on Cadence EDA tools with Day 1 focused on Analog Design (NAND gate-based schematic, simulation, and layout) and Day 2 dedicated to Digital Design (RTL synthesis, physical implementation, and GDSII generation). The sessions enriched participants’ understanding of practical VLSI workflows for research and projects.

July 17, 2025 to July 18, 2025

Venue: Room N504, B.N.M. Institute of Technology, Bengaluru

Time: 9.00am to 4:00pm