The Department of Electronics and Communication Engineering, BNMIT, in association with IEEE Circuits and Systems Society (CAS), IEEE Nanotechnology Council, and IEEE Robotics & Automation Society, organized a 3-week internship on “Design, Modeling, and Simulation of Digital Circuits using Verilog” from 21st July to 9th August 2025. The program also included Analog and Digital Design using Cadence Tools, conducted by experts from Cranes Varsity. Students gained hands-on experience in Verilog HDL, covering combinational and sequential circuits, FSMs, counters, and arithmetic circuits, along with testbench creation, functional verification, and synthesis techniques for real-world applications.

July 21, 2025 to August 09, 2025

Venue: Room N505, B.N.M. Institute of Technology, Bengaluru

Time: 9.00am to 4:00pm