The Department of ECE, BNMIT, in association with NXP Semiconductors, organized a webinar under the NXP Campus Connect initiative on SRAM and ROM IP Architecture and Design on 2nd September 2025. The session was delivered by Mr. Rajat Kohli, Sr. Principal Engineer / Design Manager e-Memories, NXP Semiconductors. The webinar introduced participants to the basic building blocks, operations, and functionality of SRAM and ROM IPs, while also highlighting how different architectural choices impact Power, Performance, and Area (PPA) of memory IPs.

September 02, 2025.

Venue: Room A215, B.N.M. Institute of Technology, Bengaluru

Time: 05.00 to 6.00pm