The internship provided hands-on exposure to VLSI design flow, Verilog RTL coding, AXI4 protocols, and SystemVerilog-based verification methodologies. Participants also gained practical understanding of assertions, functional coverage, and the basics of UVM.

The internship strengthened students’ practical skills in RTL design and SystemVerilog-based functional verification. Participants developed hands-on verification skills and were equipped to undertake VLSI design and verification projects.

Date & Time: 13.07.2026 onwards | 9:00 AM – 4:00 PM

Venue: N502 , B.N.M. Institute of Technology